The US interconnection queue held over 2,600 GW of proposed capacity in 2023, with typical waits of five years or more. AI datacentres are now the fastest-growing source of new demand the queue has to absorb.
Microsoft, 2026
Single-sourcePower delivery is built to last 15–25 years. Racks have gone from under 20 kW in the web era to more than 150 kW today, with roadmaps approaching 1 MW by 2027.
Sun et al. (Stanford / Microsoft Azure Research), 2026
The IEA projects datacentre electricity use roughly doubling from 485 TWh in 2025 to about 950 TWh by 2030, with AI-focused facilities tripling.
IEA, cited in Patel et al., 2026
Bringing one leading-edge chip fab to the US rather than Taiwan costs roughly $3–5 billion in incentives; in ten years it will cost about three times as much.
CSET, 2022
Better chips per watt, smarter power, light instead of copper: the returns the hardware research can measure.
Google's TPU v4 outperforms TPU v3 by 2.1× and improves performance per watt by 2.7×; its 4,096-chip supercomputer is nearly 10× faster overall.
Jouppi et al. (Google), ISCA, 2020
Peer-reviewedNVIDIA's Blackwell power profiles save up to 15% energy while holding performance above 97% for critical applications, raising throughput up to 13% in a power-capped facility.
Narayanaswamy et al. (NVIDIA), 2025
Company-reportedHigh-radix photonic interconnects give 2.1–3.2× lower latency in stressed high-batch regimes and 2.8–5.8× over baselines when communication is the limit.
Madhavan et al. (Lightmatter), 2026
Peer-reviewedAn optical-circuit-switched design, InfiniteHBD, matches NVIDIA's NVL-72 high-bandwidth domain at 31% of its cost and lifts model FLOPs utilisation 3.37× over a DGX cluster.
Fu et al. (ACM SIGCOMM), 2025
Peer-reviewedA traffic-aware reconfigurable optical interconnect, Vermilion, provably achieves at least 33% more worst-case throughput than existing designs.
Cao et al., 2025
Single-sourceThe optical circuit switches that let Google route around failures cost under 5% of the TPU v4 supercomputer's capital cost and under 3% of its power.
Jouppi et al. (Google), ISCA, 2020
Peer-reviewed3D-integrated photonic links move data at about 4.3 pJ per bit end to end, comparable to passive copper and far below the >20 pJ/bit of pluggable optics.
Madhavan et al. (Lightmatter), 2026
Peer-reviewedA foundry-compatible silicon-photonics MEMS switch holds its state at about 20 nanowatts with under 1.5 dB insertion loss: near-zero-power optical switching.
UC Berkeley, 2026
Single-sourceNo verified figure exists for how much of an efficiency saving is kept by the operator rather than spent on more computing. The papers report savings per job, not what happens to them.
No verified figure exists for the lifetime of today's photonic interconnects in production. Every result above is from a lab, a pilot or a single deployment.
Waste that design can remove, specs that silicon doesn't honour, and supply concentrated in a few places.
Running the same jobs, InfiniteHBD wasted 0.53% of GPUs, against 7.56% for TPUv4 and 10.04% for NVL-72.
Fu et al. (ACM SIGCOMM), 2025
Peer-reviewedNVIDIA's B300 lists INT8 support, but the silicon rate-limits it to about 1/30 of FP8, and neither vLLM nor SGLang ships a working INT8 path for it.
Chen et al., 2026
Single-sourceLeading-edge logic, legacy logic and memory each sit mostly in one or two places; the US has minimal onshore DRAM capacity and none at the leading edge.
CSET, 2022
CorroboratedAs DRAM, including the HBM feeding AI accelerators, moves to smaller nodes, RowHammer bitflips happen with about 10× fewer row activations than a decade ago.
Olgun, Kim et al., 2023
CorroboratedEven with raw HBM bit error rates up to 10⁻³, a fault-managed system kept 78% of throughput with at least 97% accuracy: one route to cheaper memory.
Bae et al., 2025
Single-sourceNo verified figure exists for what the interconnection queue costs the projects stuck in it. Estimates circulate, but none traces to a disclosed method.
No verified figure exists for how often new optical and memory components fail in production fleets. The published results are from controlled evaluations.
Costly memory, slow fabs, networks that collapse under new workloads and power capacity left stranded.
Stacking and yield sensitivity drive High-Bandwidth Memory to at least 5–10× the cost per bit of conventional DRAM, a gap that grows as AI work becomes memory-bound.
Bae et al., 2025
Single-sourceThe time to build a new US fab rose 38%, from an average of 665 days in the 1990s to 918 days in the 2010s.
CSET, 2021
CorroboratedMoving from dense to Mixture-of-Experts training cut switching efficiency by 85.6% on a Rail-Optimized network and by 98.1% on a 3D-Torus.
Switching-efficiency study (arXiv), 2026
Single-sourceAcross realistic power-delivery designs, rack projections and inference workloads, throughput per watt varies by more than 20× while cost per watt varies by over 20%.
Sun et al. (Stanford / Microsoft Azure Research), 2026
Single-sourceInvestment analyses forecast a 160% increase in datacentre power demand over this decade, while the grid's own connection queue already runs five years.
Microsoft, 2026
Single-sourceThe US has minimal onshore DRAM manufacturing capacity and none at the leading edge, though DRAM underpins the HBM in every AI accelerator.
CSET, 2022
CorroboratedThe smallest cost-effective DRAM fab, 100,000 wafers a month or about 6% of global capacity, would need $5–10 billion in CHIPS Act funding to reshore.
CSET, 2022
CorroboratedThe memory wall, supply chokepoints and the operating details fleets do not publish.
Moving a 64-bit word from off-chip DRAM costs on the order of 1,300 to 2,600 picojoules, against a few picojoules for an on-chip floating-point operation: about three orders of magnitude.
Horowitz, cited in Patel et al., 2026
Single-sourceOf ten named points of consolidation in the semiconductor supply chain, the US holds 0% of the market in five, from leading-edge logic chips to EUV resists.
CSET, BIS submission, 2021
CorroboratedCost per watt varies by more than 20% between power-delivery designs, an impact the authors measure in billions of dollars, yet no operator discloses which design it built.
Sun et al. (Stanford / Microsoft Azure Research), 2026
Single-sourceOptical switching lets a 4,096-chip TPU v4 supercomputer keep training around its 1,000 CPU hosts, each unavailable 0.1–1.0% of the time; how other fleets cope is undisclosed.
Jouppi et al. (Google), ISCA, 2020
Peer-reviewedvLLM ships no INT8 kernel for Blackwell and fails at the first forward pass; SGLang's INT8 support stops a generation earlier. The spec sheet says otherwise.
Chen et al., 2026
Single-sourceBoth sides of this page are real and both are partial. Every figure carries its source and a confidence label, and where no verified number exists the page says so rather than approximating one. The judgement is yours.
The IEA projection and Horowitz's energy figures are cited via Patel et al., as that survey states them.
